ExpectedIT and the EIC Accelerator: Pooling a Server Rack for AI

28 October 20262,050 words11 min

An AI data centre rack is not one computer but a stack of separate servers, each with its own processors and memory, passing data to the others over a network. ExpectedIT, a company registered in Esslingen am Neckar in 2021, proposes a switch chip called LPool that sits beside every CPU and joins all of them, with their memory, accelerators, network cards and storage, into what its website calls "a single rack-scale shared host". Its slogan at a September 2026 press briefing, as reported by iTWire: "the rack is the CPU".

The EIC Accelerator selected the LPool project at its March 2025 cut-off for blended finance. CORDIS records a grant of €2,499,999, signed on 7 November 2025, for a project running from 1 December 2025 to 30 November 2027. Eleven months into that period, the chip has not been manufactured, the company's speed claims have not been shown in public, and its commercial commitments are letters of intent rather than orders.

€2.5MEIC grant for LPool, per CORDIS
Mid 2027Planned tape-out of the first chip
3Signed letters of intent, no orders

Company file

Legal entity
ExpectedIT GmbH, Stuttgart local court HRB 780303, Turmstraße 14, Esslingen am Neckar
Registered
22 July 2021, articles dated 7 June 2021, share capital €30,000
Leadership
Klas Moreau (CEO since April 2026), Burkhard Steinmacher-Burow (co-founder, CPO), Árni Ingimundarson (chief engineer), Albert Weber (CFO)
Other co-founders
Klaus Entenmann, formerly CEO of Daimler Financial Services; Alexander Schwarz, formerly of NIO Europe and Airbnb DACH
Staff
About 20, including 16 engineers, per the company in September 2026
Advisers
Vinton G. Cerf among others
EIC project
LPool, agreement 101247696, December 2025 to November 2027, blended finance

What LPool is meant to do

The company's case starts from a claim on its website and in the CORDIS summary: over the past decade, on-chip performance grew 100 times faster than the movement of data between chips, so processors spend time waiting. Today a CPU in one server reaches memory or a GPU in another server through network cards and switches. LPool is meant to replace that path with a direct, cache-coherent link, so that every processor in the rack can address the whole rack's memory and devices.

Both trade reports from the briefing describe the same design. One LPool chip sits next to each CPU on the motherboard and uses the CPU's standard PCIe electrical interface with a thin protocol layer on top, and cables join the boards across the rack. ITdaily and iTWire both report that it is built on Intel's UPI processor-to-processor protocol, which Intel licensed to ExpectedIT a few weeks before the briefing; iTWire quotes Moreau saying that Intel is not licensing LPool itself. CORDIS describes two proprietary chip logic units, an LP-CPU (a CPU with what the website calls minimally modified input and output logic) and the Pool chip, plus a new server package.

The roadmap

Ten sockets first, 96 later, none built yet

How many CPU sockets each planned LPool chip generation is meant to join into one system. Generation 1 shares memory only; generations 2 and 3 run over PCIe Gen 6 and Gen 7. All three are plans.

iTWire, 2 September 2026; ITdaily, 1 September 2026.

The roadmap the company presented has three generations: up to 10 sockets with memory sharing only, then 48 over PCIe Gen 6, then 96 over PCIe Gen 7. Two limits are on the record in both reports. Existing servers cannot be upgraded, because LPool needs a purpose-built motherboard, which means server makers such as Supermicro, Dell, HPE and Lenovo would have to design one; ITdaily reports that none has signed on. And the chip needs a process of about 6 nanometres, which only TSMC, Samsung or Intel can supply.

The performance figures are the company's

ExpectedIT's figures vary by document. CORDIS says data-intensive jobs could run up to 10 times faster, with up to a halving of cost, energy and emissions per job. The website says up to 9 times faster and up to 50% less cost and CO2. At the September briefing the headline was up to 50% more AI tokens from the same hardware. ITdaily notes that the 50% claim is unproven; an AI workload demo comparing systems with and without LPool was due by the end of September 2026, according to both reports, and a web search on 28 October 2026 found no published result.

What the company says

Jobs up to 9 or 10 times faster, up to 50% lower cost and CO2, compatibility with NVIDIA, AMD, Intel, Arm and RISC-V hardware, five licensees and more than €110 million of royalties by 2031.

What can be checked

A CORDIS-reported 100,000-plus simulation runs of the Verilog code, memory directory logic through an initial TSMC N6 backend step and PCIe device sharing shown on FPGA, all per the company; no published benchmark, no chip, no signed OEM.

What the EIC project promised

According to CORDIS, the grant pays for finishing the complete logic of the Pool chip and the LP-CPU and the server package design, growing the team to 30 and widening go-to-market work. The business model is licensing the design to chip and data centre vendors. The project page lists two results so far: validation through more than 100,000 simulation runs, and "active discussions" with one of the world's leading chip vendors about licensing. With a year of the grant left, the scorecard can only mark what has started.

  1. Complete chip logic for Pool chip and LP-CPUIn progressMemory directory logic complete and through an initial TSMC N6 backend step, per the company to iTWire; verification against a real Intel CPU not started.
  2. Server package designNot shownNo board or package has been shown publicly; OEM partners are still needed.
  3. Team of 30About 2020 people including 16 engineers in September 2026, per the company's deck and ITdaily.
  4. First licenseeNot yetIntel licensed its UPI protocol to ExpectedIT, the reverse direction; the deck plans a first CPU vendor licence in 2027.

Letters of intent, not orders

The company's September 2026 deck marks three letters of intent as signed: the London AI developer FractalBrain as a design partner, Core42, the sovereign cloud arm of G42, and the Icelandic hosting company 1984 ehf for a pilot. A letter of intent from the European CPU designer SiPearl is marked pending on two slides and signed on another. ITdaily lists the three as letters of intent and states plainly that they are not orders, and describes talks with AMD and Arm as discussions with nothing concrete. The deck also quotes an unnamed Microsoft vice president calling LPool "truly new"; the person is not identified, so the quote cannot be checked.

What the register shows, and what it does not

A register extract lists the company as active, registered on 22 July 2021, with Burkhard Steinmacher-Burow as managing director with sole power of representation. It shows amended articles filed in August 2023 and February 2024 and shareholder lists from 2023, whose contents are not displayed, and no insolvency notice. No filed annual accounts could be read for this article, so the staff and capital figures here come from the company alone. Whether Klas Moreau has been entered as a managing director could not be verified from the extract.

A €2.5 million grant inside a €100 million plan

In its July 2025 announcement the company said it had received €2.5 million from the EIC Accelerator "with an option for additional equity co-financing of €10 million", and headlined the total as €12.5 million of EU funding. CORDIS records the grant only. The equity is not yet invested: the deck presents it as up to €10 million inside a €25 million Series A scheduled to open in October 2026 and close by the end of March 2027, and no EIC Fund investment in ExpectedIT has been announced. The deck gives €6.5 million of seed capital, lasting until September 2027, without naming the investors, and iTWire reports that the company puts its total capital need at €100 million to €120 million, including about €10 million for the tape-out and a €60 million Series B in late 2028 or early 2029.

The money

The EIC grant is a small slice of a €100M plan

Only the EIC grant is a recorded figure. The seed total is the company's, without named investors; the equity option and the two rounds are targets. The company puts its total need at €100M to €120M.

CORDIS (grant); ExpectedIT IT Press Tour deck and iTWire, 2 September 2026 (all other figures). Values in € millions.

The revenue forecast in the deck, as reported by iTWire, runs from €5 million in 2028 to €398 million in 2032. These are the company's projections for a product that has not been made. iTWire quotes Moreau saying that US investors told him the company is "asking for too little", and ITdaily quotes him calling the plan "a gamble" whose traction he will only trust "once the A-round is finalized".

The record

Five years from registration to a first chip, if the plan holds

Dates up to September 2026 are recorded events; later dates are the company's own plan as presented to the IT Press Tour.

  1. Jul 2021Company registeredExpectedIT GmbH entered at the Stuttgart local court, HRB 780303, with €30,000 share capital
  2. Nov 2024Vint Cerf on the advisory boardAnnounced by the company; Cerf co-designed the TCP/IP protocol
  3. Jul 2025EIC award announcedThe company announces a €2.5M EIC Accelerator grant with an option on €10M of equity€2.5M
  4. Dec 2025LPool project startsGrant agreement 101247696, signed 7 November 2025, runs to 30 November 2027
  5. Apr 2026New CEOKlas Moreau takes over as CEO; co-founder Burkhard Steinmacher-Burow becomes CPO
  6. Aug 2026Intel UPI licenceSigned weeks before the IT Press Tour, per iTWire and ITdaily
  7. Mar 2027Series A closeTarget for a €25M round scheduled to open in October 2026Planned
  8. Mid 2027Tape-outFirst LPool chip sent for manufacture, at an estimated cost of about €10MPlanned
  9. 2028First OEM machinesBest case for servers from partners, per the CEOPlanned

Commercial register extract (online-handelsregister.de); CORDIS; ExpectedIT news page; iTWire, 2 September 2026; ITdaily, 1 September 2026.

A supercomputer team, and a famous adviser

The technical founders come from IBM. Steinmacher-Burow worked for 21 years at IBM, including on the architecture of the Blue Gene supercomputers, and Ingimundarson spent six years on IBM's POWER CPU design team and eleven years at Texas Instruments, according to the company's website and iTWire. Moreau ran the Swedish memory compression company ZeroPoint Technologies for six years after 17 years at Ericsson. The company announced Vint Cerf as an adviser in November 2024, and Handelsblatt interviewed him together with Steinmacher-Burow in November 2025 under the headline "Why the father of the internet is supporting this start-up". The public parts of that article do not say whether Cerf holds shares.

In June 2026 ExpectedIT was named in the 2026 Accelerate cohort of EuroCDP, a European venture development programme for fabless semiconductor companies; iTWire reports that it was one of 20 companies picked from 79 applications. The company told iTWire the programme could add about €16 million, a figure EuroCDP's announcement does not confirm.

Why it fits European priorities, and where it does not

The European Chips Act aims to build European capacity in chip design as well as manufacturing, and a German company designing data centre silicon and licensing it to processor makers sits squarely in the design half of that aim. The supply chain does not stay in Europe: ITdaily points out that the 6 nanometre process the chip needs is offered only by TSMC, Samsung and Intel, so the chips would be made outside the EU. The deck's pending letter with SiPearl, a European server CPU designer, would tie LPool to a European processor.

The commercial obstacle is the one ITdaily names: Nvidia could impose NVLink because it sells its own GPUs, while ExpectedIT owns no CPUs, motherboards or factory and must convince Intel, AMD, server makers and hyperscalers. iTWire adds that Nvidia has opened NVLink Fusion to third-party CPUs, which could narrow ExpectedIT's window, and that CXL memory pooling competes for the same problem.

Verdict

ExpectedIT has a credible team, a signed EIC grant, an Intel protocol licence and three letters of intent, and it has said plainly that the plan rests on raising a Series A and getting a chip made. What the EIC is paying for, finished chip logic and a server design, is under way but not yet visible, and the figures that would justify the bet, measured speed-ups on real AI workloads, have not been published. Until the tape-out planned for mid-2027, LPool is a design on simulation and FPGA.

ExpectedIT was not asked for comment for this article. The reporting is based on publicly available sources, listed below.

Industry

Electronics and semiconductorsSemiconductors

Focus
  • Semiconductor IP
  • Processors
Technologies
  • Semiconductor design
  • High-performance computing
Keywords
  • Data centres
  • AI inference
  • Hyperscalers
  • Server processors
  • Interconnects
  • Memory pooling
  • Energy-efficient computing