SEMRON's EIC Accelerator Chip Stacks AI Compute Like Flash Memory

21 October 20261,002 words6 min

Large language models need far more memory and compute than a phone or a pair of glasses can offer. Edge devices typically allow less than one square centimetre of silicon and less than one watt of continuous power, and today's chips fit models of a few million parameters in that budget, not billions, according to the CORDIS summary of SEMRON's EIC project. The Dresden start-up proposes to compute with capacitors inside a 3D structure borrowed from flash memory, so that hundreds of compute layers sit on one die.

The EIC Accelerator selected the project, Aloe AI, at its October 2024 cut-off under the challenge "Enabling the smart edge", and CORDIS records a grant of €2,499,999 from January 2025 to December 2026 to build a demonstrator of the 3D-stacked inference chip. Two months before the end of the project, no demonstrator has been shown in public, and CORDIS lists no report.

€2.5MEIC Accelerator grant for Aloe AI
3,500+TOPS per watt on a 156-cell test array, 2021
Dec 2026Scheduled end of the EIC project

Company file

Legal entity
SEMRON GmbH, Amtsgericht Dresden HRB 39815
Registered
4 February 2020; share capital €46,541
Headquarters
Frauenstraße 9, Dresden; hiring also in Austin, Texas
Founders
Aron Kirschen (CEO), Kai-Uwe Demasius (CTO)
Investors
Join Capital, SquareOne, OTB Ventures, Onsight Ventures (Hermann Hauser), Gigahertz Ventures, BlueWonder
Advisers
Hans Rohrer (former president of TSMC Europe), Hermann Hauser (founder of Arm), Alex Kalnitsky, Pieter Abbeel, Boris Murmann
EIC project
Aloe AI, agreement 101218503, January 2025 to December 2026

Record efficiency in a lab array

SEMRON's founders built the technology in research before the company existed. In October 2021 CTO Kai-Uwe Demasius, CEO Aron Kirschen and Stuart Parkin of the Max Planck Institute of Microstructure Physics published a memcapacitor device in Nature Electronics. A prototype crossbar array with 156 memory cells ran a small image recognition task, classifying the letters M, P and I, at more than 3,500 tera-operations per second per watt at 6 to 8 bit precision, and a handwritten digit task reached 29,600 TOPS/W, which the institute called the highest efficiency reported for a neuromorphic system at that precision. The design was shown to scale to 45-nanometre devices in simulation.

Those results come from a small array, not a chip that runs a language model. The step from 156 cells to a product with hundreds of stacked layers is what the company and the EIC project are about.

Lab results

Record efficiency on a 156-cell test array

Measured and simulated efficiency in the 2021 paper, on a small crossbar array; not a full chip.

Demasius, Kirschen and Parkin, Nature Electronics 4, 748 to 756 (2021), via the Max Planck Institute. Values in tera-operations per second per watt.

Computing inside 3D flash

CapRAM, as SEMRON calls its technology, computes with variable capacitors rather than with currents through transistors, which it says gives a better signal-to-noise ratio than resistive in-memory computing and keeps heat down as compute density rises. The compute layers are to be grown with the established 3D NAND flash process, which already stacks hundreds of memory layers, and the project claims this could cut the cost per unit of performance by two orders of magnitude. The company website makes the point with 256 layers: memory already fits that many on silicon, compute only one.

What the company says

A 20-fold gain in chip-level energy efficiency, models 200 to 300 times larger than today and up to 1,000 times, and a cost per performance two orders of magnitude lower.

What the record shows

A 2021 paper on a 156-cell array, an IEEE paper and a performance pre-print on request, and no public demonstrator chip or customer.

The record

A 2021 Nature paper, a 2024 seed round and an EIC project ending in 2026

The EIC project is due to end on 31 December 2026; no demonstrator chip had been shown publicly by October 2026.

  1. Feb 2020Company registeredSEMRON GmbH, HRB 39815, Dresden
  2. Oct 2021Nature Electronics paperMemcapacitor crossbar with 156 cells, over 3,500 TOPS/W at 6 to 8 bits
  3. Jan 2024Seed roundJoin Capital leads with SquareOne, OTB Ventures and Onsight Ventures; total funding €10M€7.3M
  4. Oct 2024EIC Accelerator cut-offAloe AI selected under the smart edge challenge
  5. Jan 2025Aloe AI startsDemonstrator of a 3D-stacked inference chip€2.5M
  6. 2026US hiringJob boards for Austin, Texas, and Dresden on the company website
  7. Dec 2026Aloe AI endsScheduled end of the EIC projectScheduled

Implisense (Dresden register), Max Planck Institute of Microstructure Physics, tech.eu, CORDIS, SEMRON website.

A €7.3 million seed and the EIC grant

In January 2024 SEMRON raised a €7.3 million seed round led by Join Capital with SquareOne, OTB Ventures and Hermann Hauser's Onsight Ventures, bringing its total funding to €10 million, tech.eu reported. Pre-seed investors included Wolfram Drescher, Gigahertz Ventures and Hans Rohrer. The money was for hardware and compiler development and a larger team. No later round has been announced, and whether the EIC Fund has invested the equity part of the blended award is not public. The company has no public annual statements on file with the data service Implisense.

Funding

€12.5M in total, a fifth of it from the EIC

Pre-seed money derived from the €10M total announced in January 2024; no later round has been announced.

tech.eu, 30 January 2024; CORDIS. Values in € millions.

Aloe AI before its end date

The Commission signed the grant on 18 June 2025, almost six months after the project's official start on 1 January 2025. CORDIS shows no periodic report and no result, and SEMRON has not announced a demonstrator. Its website points to an IEEE paper and offers a performance pre-print on request, and it advertises jobs in Dresden and Austin, Texas.

  1. CapRAM deviceShown in researchNature Electronics 2021, 156-cell array.
  2. 3D-stacked compute layers in a flash processNot publicNo published stack or test chip.
  3. Demonstrator running LLMs at the edgeNot publicNo demonstrator announced; project ends December 2026.
  4. CustomersNone namedNo partner or customer announced.

An AI chip from Dresden

An AI inference chip designed in Dresden and built on a standard memory process would fit the EU's push for its own semiconductor capabilities, and the EIC funded it under its challenge for the smart edge. SEMRON's advisers include the founder of Arm and a former president of TSMC Europe. The company is also hiring in Austin, Texas.

Verdict

SEMRON rests on a strong 2021 result and has assembled distinguished advisers and €10 million of private money. The EIC paid for the step from a lab array to a demonstrator chip, and with the project ending in December 2026, that demonstrator has not been shown. Until it is, the 3D CapRAM chip remains a promising idea rather than a product.

Industry

Electronics and semiconductorsSemiconductors

Focus
  • Processors
Technologies
  • Semiconductor design
  • Edge computing
Keywords
  • Edge AI
  • Large language models
  • In-memory computing
  • Neuromorphic computing
  • AI chips